This digital semiconductor validation test system is designed to test the digital characteristics of a CMOS semiconductor chip. It comprises a hardware and software component. Here you will find detailed information and example code to perform memory tests and bit error rate tests (BERT) on a CMOS chip.
The system hardware consists of a source measure unit (SMU) and a high-speed digital board. The SMU powers the device under test (DUT). The high-speed digital board provides the ability to communicate and exercise the DUT with stimulus signals as well as measure the DUT's response to these signals. Tests performed include the bit error rate test (BERT) and memory tests.
The system software consists of test code and test management sequence. The test code is used to configure hardware devices for appropriate measurements. It is also used for data processing and analysis. Each test is written as a separate module. The test management sequence organizes individual test code modules and provides a framework for adding more tests in the future.
Once you've explored the diagram, select Architecture Details for more information.