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IPNet - LabVIEW FPGA Functions and Example IP

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Overview

The LabVIEW FPGA IPNet is your one-stop resource for browsing, understanding, and downloading LabVIEW FPGA functions or IP (intellectual property). The table below is a collection of FPGA IP and examples gathered from the LabVIEW FPGA function palette, internal National Instruments developers, and the LabVIEW FPGA community. You should use this resource to acquire IP that you need for your application, download examples to help learn programming techniques, and explore the depth of IP offered by the LabVIEW FPGA platform. In addition to exploring what is offered here, you can also share your LabVIEW FPGA IP or submit an update to existing IP for the LabVIEW community by clicking the link below.



Note:
Code Maturity of 1 = unreleased or untested code. Minimum flexibility and/or usability.
Code Maturity of 5 = fully tested, shipping IP. Maximum flexibility and usability.

* indicates example or IP is coming soon.




Table of Contents

  1. Math
  2. Signal Processing and Measurements
  3. Data Manipulation, Transfer, and Storage
  4. RF and Communications
  5. Data Acquisition and Triggering
  6. Signal Generation
  7. Control
  8. Digital Buses and Protocols
  9. Simulation
  10. Encryption
  11. Image Processing
  12. Submit Your LabVIEW FPGA IP or Example Program

Discuss and Request: IPNet Forum Thread

Style Guidelines for FPGA IP: LabVIEW FPGA Design for Code Modules (IP Cores)

Integrate 3rd Party HDL IP with CLIP:  Integrate IP using CLIP (tutorial), CLIP XML Wizard 

FPGA Module Concepts: LabVIEW FPGA Manual

LabVIEW FPGA Training Module: LabVIEW FPGA Training Material

 

Math

Name
LabVIEW Version
IP or Example
Source
Code Maturity

Multiply (FXP Library)

8.5,8.6

IP

Developer Zone

5
 Multiply (LV FPGA) 8.6 IP LabVIEW FPGA 5

Divide (FXP Library)

8.5,8.6

IP

Developer Zone

5
 Divide (LV FPGA) 8.6 IP LabVIEW FPGA 5
 Divide (INT Scaling) 8.0 Example Developer Zone 3

Reciprocal (FXP Library)

8.5,8.6

IP

Developer Zone

5
 Reciprocal (LV FPGA) 8.6 IP LabVIEW FPGA 5

Square Root (FXP Library)

8.5,8.6

IP

Developer Zone

5
 Square Root (LV FPGA) 8.6 IP LabVIEW FPGA 5

Sine

8.5,8.6

IP

Developer Zone

5

Cosine

8.5,8.6

IP

Developer Zone

5
 Inverse Sine (aSin)
 8.6 IP Community 4
 Inverse Sine (aSin - Four Quadrant) 8.6 IP Community 4

Arctangent2

8.5,8.6

IP

Developer Zone

5

Polar To Rectangular

8.5,8.6

IP

Developer Zone

5

Rectangular To Polar

8.5,8.6

IP

Developer Zone

5

Hyperbolic Sine

8.5,8.6

IP

Developer Zone

5

Hyperbolic Cosine

8.5,8.6

IP

Developer Zone

5

Exponential

8.5,8.6

IP

Developer Zone

5

Natural Logarithm

8.5,8.6

IP

Developer Zone

5

FXP AddSub

8.5,8.6

IP

Developer Zone

5

Integer Accumulator

8.5,8.6

IP

Developer Zone

5
 Multiply Accum (Virtex5 DSP48E) 8.5 IP Developer Zone 4

Scale by Power of Two

8.5, 8.6

IP

LabVIEW FPGA

5

Numeric Rounding

8.5, 8.6

IP

LabVIEW FPGA

5
 Linear Interpolation 8.5, 8.6 IP LabVIEW FPGA 5

Pseudo-Random Number Gen

8.2

IP

Community

3

Linear Fit Regression (PtByPt)

8.5

IP

Community

3

Temperature Conversion

8.5

IP

Community

2

2n Point-by-Point Average

8.5

IP

Community

2

2n Point Moving Average

8.5

IP

Community

3

8-Point Average (Parallel)

8.5

IP

Community

2

Max/Min/Range (PtByPt)

8.5

IP

Community

2

Range (PtByPt)

8.5

IP

Community

3

Histogram (PtByPt)

8.5

IP

Community

3
 Fixed-array Cross-Correlation 8.6 IP Community 3
 Fixed-array Auto Correlation 8.6 IP Community 3

 

Signal Processing and Measurements

Name
LabVIEW Version
IP or Example
Source
Code Maturity

Butterworth Filter

8.2, 8.5, 8.6

IP

LabVIEW FPGA

5

Notch Filter

8.5, 8.6

IP

LabVIEW FPGA

5

Dolph-Chebyshev Filter (FIR)

8.6

IP

DFD Toolkit

5

Kaiser Window Method Filter (FIR)

8.6

IP

DFD Toolkit

5

Equi-Ripple Filter (Remez) (FIR)

8.6

IP

DFD Toolkit

5
 Time-domain Window Filter (FIR) 8.6 IP DFD Toolkit 5
 Bessel Filter (IIR) 8.6 IP DFD Toolkit 5
 Chebyshev Filter (IIR) 8.6 IP DFD Toolkit 5
 Inverse Chebychev Filter (IIR) 8.6 IP DFD Toolkit 5
 Elliptical Filter (IIR) 8.6 IP DFD Toolkit 5
 Least Pth Norm (FIR or IIR) 8.6 IP DFD Toolkit 5
 Arbitrary Group Delay Allpass Filter 8.6 IP DFD Toolkit 5
 Comb Filter (IIR) 8.6 IP DFD Toolkit 5
 Notch/Peak Filter 8.6 IP DFD Toolkit 5
 Max Flat Filter (FIR or IIR) 8.6 IP DFD Toolkit 5
 Narrowband Filter (Interpolated FIR) 8.6 IP DFD Toolkit 5
 Multirate Cascaded Integrator Comb (CIC) 8.6 IP DFD Toolkit 5
 Multirate FIR 8.6 IP DFD Toolkit 5
 Multistage Multirate Filter 8.6 IP DFD Toolkit 5
 Multirate Halfband Filter 8.6 IP DFD Toolkit 5
 Nyquist Filter 8.6 IP DFD Toolkit 5
 Raised Cosine Filter 8.6 IP DFD Toolkit 5
 Root-Raised Cosine Filter 8.6 IP DFD Toolkit 5

Adaptive Filters (LMS)

8.6

IP

AF Toolkit

5
 Octave Filter 8.5 Example Developer Zone 3

Fast Fourier Transform (FFT)

8.6

IP

LabVIEW FPGA

5
 Streaming FFT 8.6 IP LabVIEW FPGA 5
 Inverse FFT 8.6 IP LabVIEW FPGA 5
 Clarke Transform 8.6 IP Community 3
 Inverse Clarke Transform 8.6 IP Community 3
 Park Transform 8.6 IP Community 3
 Inverse Park Transform 8.6 IP Community 3

DC - Mean (DC/RMS)

8.2, 8.5, 8.6

IP

LabVIEW FPGA

5

Running Sum (DC/RMS) 

8.2, 8.5, 8.6

IP

LabVIEW FPGA

5

Running Sum of Squares (DC/RMS) 

8.2, 8.5, 8.6

IP

LabVIEW FPGA

5

Mean Square (DC/RMS)

8.2, 8.5, 8.6

IP

LabVIEW FPGA

5

Root Mean Square (DC/RMS)

8.2, 8.5, 8.6

IP

LabVIEW FPGA

5

Analog Period Measurement

8.2, 8.5, 8.6

IP

LabVIEW FPGA

5

Four Channel Gain/Attenuate

8.2

IP

Community

4

Simple Alarming

7.1

IP

Community

2
 Rational Resampling 8.6 IP LabVIEW FPGA 5
 Median Filter 8.5.1 IP Community 3
 Hanning Window 8.6 IP LabVIEW FPGA 5
 Hamming Window 8.6 IP LabVIEW FPGA 5
 Blackman-Harris Window 8.6 IP LabVIEW FPGA 5
 Exact Blackman Window 8.6 IP LabVIEW FPGA 5
 Blackman Window 8.6 IP LabVIEW FPGA 5
 Flat-Top Window 8.6 IP LabVIEW FPGA 5
 4-Term B-Harris Window 8.6 IP LabVIEW FPGA 5
 7-Term B-Harris Window 8.6 IP LabVIEW FPGA 5
 Low Sidelobe Window 8.6 IP LabVIEW FPGA 5

 

Data Manipulation, Transfer, and Storage

Name
LabVIEW Version
IP or Example
Source
Code Maturity

Direct Memory Access (DMA) FIFO

8.2, 8.5, 8.6

IP

LabVIEW FPGA

5
 VI- or Target-Scope FIFO 8.2, 8.5, 8.6 IP LabVIEW FPGA 5
 Memory Read/Write (FPGA Block RAM) 8.2, 8.5, 8.6 IP LabVIEW FPGA 5
 Split/Join Number 8.0, 8.2, 8.5, 8.6 IP LabVIEW FPGA 5
 Rotate Right/Left 8.0, 8.2, 8.5, 8.6 IP LabVIEW FPGA 5
 Swap Bytes/Words 8.0, 8.2, 8.5, 8.6 IP LabVIEW FPGA 5
 Numeric Conversion 8.0, 8.2, 8.5, 8.6 IP LabVIEW FPGA 5
 Number To/From Boolean Array 8.0, 8.2, 8.5, 8.6 IP LabVIEW FPGA 5
 Binary to BCD to ASCII 8.5 IP Community 3
 Look-up Table 8.0, 8.2, 8.5, 8.6 IP LabVIEW FPGA 5
 Array Manipulation Functions 8.0, 8.2, 8.5, 8.6 IP LabVIEW FPGA 5
 Boolean Functions 8.0, 8.2, 8.5, 8.6 IP LabVIEW FPGA 5

Simple Binary Shift Register

8.5

IP

Community

3
 Loop Benchmark Timer 8.5 IP Developer Zone 4
 Sort Array (Bubble Sort) 8.5 IP Community 3
 64X64 Virtual Digital Switch Matrix 8.5 IP Developer Zone 3
 FPGA On-chip Debug Library 8.5 IP Developer Zone 4
 Watchdog Safety Architecture 8.5.1 Example Developer Zone 4
 Biphase Manchester Encoding 8.6 IP Community 3
 16-bit cyclic redundancy checker (CRC) 8.6 IP Community 3
 8-bit Fibonacci Linear Feedback Shift Reg (LFSR) 8.6 IP Community 3

 

RF and Communications

Name
LabVIEW Version
IP or Example
Source
Code Maturity

Amplitude Modulation (AM)

8.2, 8.5

IP

Community

3
  FM Demodulation 8.5.1 IP NI Labs 4
  IQ Fractional Resampler (Upsampling) 8.5.1 IP NI Labs 4
  IQ Fractional Resampler (Downsampling) 8.5.1 IP NI Labs 4
  On-Off Keying Modulator 8.5.1 IP NI Labs 4
  On-Off Keying Demod (Burst) 8.5.1 IP NI Labs 4
  Diff. Binary Phase Shift Keying (DBPSK) Demod 8.5.1 IP NI Labs 4
  Quadrature Phase-Shift Keying (QPSK) Demod 8.5.1 IP NI Labs 4
  Reed-Solomon Encoder 8.5.1 IP NI Labs 4
  Reed-Solomon Decoder 8.5.1 IP NI Labs 4
  Viterbi Decoding 8.5.1 IP NI Labs 4
 Lock-In Amplifier 8.5 IP Community 4

 

Data Acquisition and Triggering

Name
LabVIEW Version
IP or Example
Source
Code Maturity

Balanced Analog I/O

8.2

Example

Developer Zone

4

160 Correlated DIO*

8.2

Example

Developer Zone

4

Multirate Analog Output

8.2

Example

Developer Zone

4

Buffered DAQ with DMA Streaming

8.2

Example

Developer Zone

4

Synchronous Loop Scheduler

8.5

Example

Community

3

Latching Digital Input

8.5

IP

Community

3

Digital Event Recorder

7.0

Example

Developer Zone

4

Edge Detection (Simple)

8.5

IP

Community

3

Edge detection (w/ decimation)

8.5

Example

Community

3

Custom Analog Triggering

7.1, 8.0

Example

Developer Zone

4
 Reference Triggering on FPGA 8.5 Example Developer Zone 3

Custom Digital Triggering

8.5

IP

Community

4

Hysteresis trigger

8.5

IP

Community

4

64-bit Counters

8.2

Example

Developer Zone

4

Tachometers

7.1

Example

Developer Zone

4

Pulse-Width Modulation (PWM)

8.2

Example

Developer Zone

4

Pulse Phase Shift (on-the-fly)

8.2.1

IP

Community

3

Tachometer Measure (w/hyst)

7.1

IP

Community

3

Quadrature Encoders

7.1

Example

Developer Zone

4
 Two-Edge Separation 8.6 IP Community 3
 Rising Edge Delay 8.6 IP Community 4
 Interrupt 8.0, 8.2, 8.5, 8.6 IP LabVIEW FPGA 5
 Occurance 8.0, 8.2, 8.5, 8.6 IP LabVIEW FPGA 5
 Semaphore 8.5.1 IP Developer Zone 4
 64-bit Tick Count 8.5.1 IP Developer Zone 4
 Synchronize Multiple cRIOs 8.0 Example Developer Zone 3
 cRIO Datalogging Architecture 8.5 Example Developer Zone 3

 

Signal Generation

Name
LabVIEW Version
IP or Example
Source
Code Maturity

Direct Digital Synthesis

8.5.1

Example

Developer Zone

3

Sine Wave Generation

8.0, 8.2, 8.5

IP

LabVIEW FPGA

5

Square Wave Generation

8.5

IP

LabVIEW FPGA

5

Ramp Function

7.1

IP

Community

2

Sawtooth Generator

8.5

IP

Community

3

Linear Waveforms

7.1

Example

Developer Zone

3

Nonlinear Waveforms

7.1

Example

Developer Zone

3

Periodic Waveforms

7.1

Example

Developer Zone

3

Arbitrary Waveform Generation

7.1

Example

Developer Zone

3

Uniform White Noise

8.5

IP

LabVIEW FPGA

5

Gaussian White Noise

8.5

IP

LabVIEW FPGA

5

VGA Signal Generation*

8.0

IP

Community

2

Audio Output Example*

8.0

Example

Community

2

Digital Pulse Generation

7.1

Example

Developer Zone

3

Pulse-Width Modulation (PWM)

8.2

Example

Developer Zone

4
 PWM output (Center-Aligned) 8.6 IP Community 4
 PWM Triangle wave 8.6 IP Community 4
 Space-Vector Generator 8.6 IP Community 4

 

Control

Name
LabVIEW Version
IP or Example
Source
Code Maturity

Discrete Linear Systems

Multichannel PID

8.0, 8.2, 8.5, 8.6

IP

LabVIEW FPGA

5
 PID, Analog, PWM Example 8.5 Example Developer Zone 3

Motion PID (Spline and Step)

8.0, 8.2, 8.5, 8.6

IP

SoftMotion

5

Discrete PID

8.0, 8.2

IP

LabVIEW FPGA

5
 Multi-axis Motion PID 8.5 IP Developer Zone 3
 Adaptive Gain Control Filter 8.6 IP Community 3
 Field-Oriented Controller (FOC) 8.6 Example Community 4
 Half-Bridge Controller (H-Bridge) 8.6 IP Community 4
 6-Phase (Trapezoidal) Brushless DC Motor 8.6 IP Community 4
 Spline Interpolation 8.0, 8.2, 8.5, 8.6 IP SoftMotion 5
 Look-up Table for Sinusoidal (V/f) Control 8.6 IP Community 4
 Cam/Crank Angle Measurement 8.6 Example Community 3

Discrete Control Filter

8.0, 8.2, 8.5, 8.6

IP

LabVIEW FPGA

5

Discrete Delay

8.0, 8.2, 8.5, 8.6

IP

LabVIEW FPGA

5

Discrete Normalized Integrator

8.0, 8.2, 8.5, 8.6

IP

LabVIEW FPGA

5

Initial Condition

8.0, 8.2, 8.5, 8.6

IP

LabVIEW FPGA

5

Unit Delay

8.0, 8.2, 8.5, 8.6

IP

LabVIEW FPGA

5

Zero-Order Hold

8.0, 8.2, 8.5, 8.6

IP

LabVIEW FPGA

5

Nonlinear Systems

Backlash

8.0, 8.2, 8.5, 8.6

IP

LabVIEW FPGA

5

Boolean Crossing

8.0, 8.2, 8.5, 8.6

IP

LabVIEW FPGA

5

Dead Zone

8.0, 8.2, 8.5, 8.6

IP

LabVIEW FPGA

5

Friction

8.0, 8.2, 8.5, 8.6

IP

LabVIEW FPGA

5

Memory Element

8.0, 8.2, 8.5, 8.6

IP

LabVIEW FPGA

5

Quantizer

8.0, 8.2, 8.5, 8.6

IP

LabVIEW FPGA

5

Rate Limiter

8.0, 8.2, 8.5, 8.6

IP

LabVIEW FPGA

5

Relay

8.0, 8.2, 8.5, 8.6

IP

LabVIEW FPGA

5

Saturation

8.0, 8.2, 8.5, 8.6

IP

LabVIEW FPGA

5

Switch

8.0, 8.2, 8.5, 8.6

IP

LabVIEW FPGA

5

Trigger

8.0, 8.2, 8.5, 8.6

IP

LabVIEW FPGA

5

Zero Crossing

8.0, 8.2, 8.5, 8.6

IP

LabVIEW FPGA

5

 

Digital Buses and Protocols

Name
LabVIEW Version
IP or Example
Source
Code Maturity

SPI

7.0

Example

Developer Zone

4

I2C

8.2

IP

Community

4

S/PDIF

7.1

Example

Developer Zone

4

RS-232

7.0, 8.2

Example

Developer Zone

2

HDLC

8.2

IP

Developer Zone

4

I2S

8.2

IP

Community

3

SSI

8.2

IP

Community

3

Huffman Decoder

8.2

IP

Community

3

IRIG-B

7.1

Example

Developer Zone

3

PCM Telemetry

7.1

Example

Developer Zone

3

UART

8.5

IP

Community

3
 Direct Stream Digital® Decode 8.5 Example Developer Zone 3

Clock Division

8.5

IP

Community

3

Custom Serial Protocol

8.0

Example

Developer Zone

3
 Num to 7-Segment LED 8.5 IP Community 3
 1-wire protocol (DS2432) 8.5 IP Community 3
 Hitachi HD44870-based LCD 8.6 Example Community 4

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